The invention relates generally to voltage-controlled oscillators (VCOs) and more, and more particularly to variable duty-cycle pulse-width modulated VCOs.
Voltage-controlled variable duty-cycle oscillators are found in many applications. FIG. 1, for example, depicts a DC:DC converter 10 that receives an input voltage Vin and delivers an output voltage Vout to a load coupled in parallel with output filter capacitor Co. A feedback loop that includes path 20 provides a resistor-divided R1, R2 fraction of Vout as one input to a fixed gain 15 error amplifier 30. The other input to error amplifier 30 is coupled to Vref, a precision voltage reference source 40, for example a 1.20 VDC bandgap voltage reference. If magnitude of Vout is too low, Vref will be greater than the fraction of Vout coupled to error amplifier 30, and if magnitude of Vout is too high, Vref will be less than the Vout fraction coupled to the error amplifier.
The error output signal (Verr) from amplifier 30 is coupled as an input to comparator 50. Comparator 50 has two inputs, and the other input is coupled to receive a sawtooth output waveform from oscillator 60, for example a 200 KHz sawtooth waveform. The output from comparator 50 is a voltage-controlled variable duty cycle signal. This comparator 50 output signal is input to a driver 70 whose output pulse train is coupled to the input of solid state switch Qs, whose buffered output appears at the emitter of transistor Qout. The Qout emitter signal is low-pass filtered by L1 and capacitor Co. Diode D1 serves to provide a current path during intervals that Qs is turned-off by driver 70.
In the configuration of FIG. 1, Qs and Qout are shown coupled both to an internal regulator 80 and to Vin. Internal regulator 80 can serve to provide operating potential to converter 10 to sustain operation immediately upon power-up to the converter. Further, an input signal coupled to regulator 80 can serve as a mechanism to shut-down operation of converter 10, should the need arise. Note in figure one that a limit circuit 90 is coupled to comparator 50 to establish a minimum and a maximum desired duty cycle for switching of transistor Qs. Limit circuit 90 may be implemented by imposing voltage clamps on the output excursion(s) of comparator 50, or by using digital control techniques. Also shown in FIG. 1 but not here relevant are protective circuit 100 to limit output current for converter 10 and protective circuit 110 to invoke thermal shutdown of the converter.
Assume that Vout is too high in magnitude. Converter 10 senses this error and lowers Vout in the following manner. If Vout is too high, then the fraction of Vout fed back to error amplifier 30 will also be too high, which means the magnitude of Verr will increase. Thus when Verr is compared against the oscillator 60 sawtooth waveform, comparator 50 will detect only the peak portions of the sawtooth waveform. As a result, duty cycle of the comparator output signal, and thus duty cycle associated with switching of transistor Qs, will decrease. Vout will be proportional to the product of (Vin) and (duty cycle), and a decrease in duty cycle will decrease Vout, which is the desired result. On the other hand, if Vout were too low, the fraction of Vout compared against Vref by error amplifier 30 will be too low, and Verr will decrease in magnitude. When comparator 50 compares Verr against the sawtooth waveform from oscillator 60, the comparator will change state at a lower region of the sawtooth waveform, which is to say duty cycle will increase. The increase in duty cycle will increase magnitude of Vout.
While DC:DC converters implemented as shown in FIG. 1 find widespread use, comparator 50 must operate quite rapidly, even with modest amounts of signal overdrive. In brief, comparator 50, especially a rapidly operating integrated circuit comparator can be a relatively expensive component. For example, dual input comparator 50 must typically be implemented with several transistors. Further, since magnitude of the output signal from the comparator dictates converter duty cycle, a limiting circuit 90 is needed to guard against too low or too high a duty cycle.
There is a need for a somewhat simplified voltage-controlled variable duty-cycle oscillator system, including a DC:DC converter system, that preferably operates with a comparator that can be implemented with as few as two transistors. Further, for use with such a system, the minimum or maximum output duty cycle controlled by the comparator should be controlled by a simple ratio of passive components, for example a capacitor ratio.
The present invention provides such a voltage-controlled variable duty-cycle oscillator system, and comparator.
A voltage-controlled variable duty-cycle oscillator includes a reference current generator in which a resistor R1 determines magnitude of a current Iref that is mirrored in a first one-shot, in a second one-shot, and in a third one-shot. The oscillator further includes pre- and post-logic circuits, preferably implemented using NOR gates. Each one-shot includes two pair of series-coupled MOS transistors and a timing capacitor. In the first and second one-shots, the timing capacitor (C1, C2) is precharged to Vcc, and in the third one-shot, the timing capacitor (C3) is precharged to a control voltage Vcon less than Vcc. A ramp-like voltage is developed across each timing capacitor, proportional in part to the mirrored current Iref that is established by resistor R1. If desired, one-shot operation could in essence be inverted to charge up timing capacitors from ground to Vccxe2x88x92Vth (for a PMOS device). However the same timing relationships would still be applicable.
Within each one-shot, a series-coupled MOS transistor pair functions as a two-transister comparator circuit. Advantageously, one-shot time-out duration is determined substantially solely by the associated timing capacitor value and the resistor-determined mirrored current magnitude. Output signals from the first and second one-shot are coupled as inputs to the pre-logic circuit whose output is an intermediate oscillator signal OSCint. The duty cycle of the OSCint signal is determined by Iref and by the timing capacitor associated with the first and second one-shot. In the third one-shot, the associated timing capacitor is precharged to Vcon and time-out for this one-shot is determined substantially solely by magnitude of Vcon.
The output of the third one-shot and the intermediate oscillator signal are input to the post-logic circuit, whose output signal VCOout is the desired variable duty cycle voltage-controlled oscillator (VCO) output signal. Leading edges of the intermediate oscillator signal OSCint are not affected by the post-logic circuit, but the trailing edge of the post-logic output signal is affected by magnitude of the Vcon voltage used to precharge the timing capacitor C3 associated with the third one-shot. If Vcon less than Vcc, then the maximum duty cycle of the VCO output signal is determined by the ratio of the timing capacitor in the third one-shot compared to the sum of the timing capacitors in the first and second one-shots, e.g., by C3/(C1+C2). Minimum duty cycle for the VCO output signal can be zero if Vcon less than Vth (threshold voltage) for MOS device in the third one-shot whose gate is coupled across the associated timing capacitor. Advantageously, VCO output signal duty cycle is a very linear function of Vcon.